Taiwan Semiconductor Manufacturing Comp. Ltd.

Shau-Lin Shue

Ming-Han Lee

Hsin-Yen Huang

Chung-Ju Lee

Shin-Yi Yang

Shao-Kuan Lee

Hai-Ching Chen

Cheng-Chin Lee

Tien-I Bao

Yung-Hsu Wu

Chen-Hua Douglas Yu

Hsiang-Huan Lee

Cheng-Hsiung Tsai

Ru-Gun Liu

Chung-Shi Liu

Chia-Tien Wu

Chi-Lin Teng

Ting-Ya Lo

Ching-Hua Hsieh

Mei-Yun Wang

Chih-Wei Chang

Hsin-Ping Chen

Chao-Hsien Peng

Tsai-Sheng Gau

Hsiao-Kang Chang

Tai-I Yang

Chii-Ming M Wu

Cherng-Shiaw Tsai

Jing-Cheng Lin

Ming-Hsing Tsai

Cheng-Lin Huang

Ming-Feng Shieh

Hsin-Chieh Yao

Wen-Chih Chiou

Mong-Song Liang

Chun-Kuang Chen

Yung-Sung Yen

Chih-Ming Lai

Shih-Ming Chang

Hsi-Wen Tien

Weng-Jin Wu

Kuei-Shun Chen

Tsung-Min Huang

Wei-Chen Chu

Carlos H Diaz

Chih Wei Lu

Cheng-Tung Lin

Hsiang-Wei Liu

Hung-Wen Su

Yung-Chih Wang

Chia-Shiung Tsai

Ming-Fa Chen

Syun-Ming Jang Jang

Jyu-Horng Shieh

Ken-Hsien Hsieh

Hsien-Ming Lee

Chia-Ying Lee

Shing-Chyang Pan

Chien-Hua Huang

Min Cao

Minghsing Tsai

Ching-Fu Yeh

Wei-Hao Liao

Ken-Ichi Goto

Chih-Wei Lu

Jih-Churng Twu

Ming-Shih Yeh

Yu-Teng Dai

Hsin-Hsien Lu

Kai-Fang Cheng

Ting-Chu Ko

Chung-En Kao

Hun-Jan Tao

Tsang-Jiuh Wu

Chun-Chieh Lin

Yung-Chi Lin

Ying-Ho Chen

Wei-Jung Lin

Tsu Shih

Ming-Huan Tsai

Chia-Wei Su

Hung-Pin Chang

Chiang-Ming Chuang

Ju-Wang Hsu

Horng-Huei Tseng

Chao-Cheng Chen

Ying-Lang Wang

Yung-Cheng Lu

Chao-Hsiung Wang

Chung-Chi Ko

Tien-Lu Lin

Ku-Feng Yang

Liang-Guang Chen

Hung-Chang Hsieh

Kuei Shun Chen

Chu-Yun Fu

Ming-Hsien Lin

Shih-Chi Lin

Yuan-Hung Chiu

Chia-Lin Yu

An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line in a first dielectric layer, a catalyst layer on the first dielectric layer, a dielectric block on the catalyst layer, an etching stop layer along the second metal line, the catalyst layer and the dielectric block, a second dielectric layer over the etching stop layer, and a first via through the second dielectric layer and the etching stop layer on the first metal line. A first interface between the etching stop layer and the second metal line is level to a second interface between the catalyst layer and the first dielectric layer.

Interconnect structure and method for forming the same

A method for manufacturing a semiconductor device includes preparing an electrically conductive structure including a plurality of electrically conductive features, conformally forming a thermally conductive dielectric capping layer on the electrically conductive structure, conformally forming a dielectric coating layer on the thermally conductive dielectric capping layer, filling a sacrificial material into recesses among the electrically conductive features, recessing the sacrificial material to form sacrificial features in the recesses, forming a sustaining layer over the dielectric coating layer to cover the sacrificial features, and removing the sacrificial features to form air gaps covered by the sustaining layer. The thermally conductive dielectric capping layer has a thermal conductivity higher than that of the dielectric coating layer.

Semiconductor device having thermally conductive air gap structure and method for manufacturing the same

An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.

Semiconductor interconnection structure and methods of forming the same

A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.

Semiconductor device having metallization layer with low capacitance and method for manufacturing the same

An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

Semiconductor device structure and methods of forming the same

A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.

Semiconductor structure with improved heat dissipation

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.

Self-align via structure by selective deposition

An interconnect structure is provided. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a capping layer having a first portion, a second portion opposing the first portion, and a third portion connecting the first portion and the second portion, wherein the third portion is in contact with the dielectric layer. The structure also includes a support layer in contact with the first and second portions of the capping layer, a first conductive layer disposed over the first conductive feature, a second conductive layer disposed over the dielectric layer, and a two-dimensional (2D) material layer in contact with a top surface of the first conductive layer, wherein the support layer, the first portion, the second portion, and the third portion define an air gap, and the air gap is disposed between the first conductive layer and the second conductive layer.

Semiconductor device structure having air gap and methods of forming the same

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

Semiconductor packages and methods for forming the same

A semiconductor structure includes a contact over a substrate, an interlayer dielectric (ILD) layer including a first region disposed directly above the contact and a second region disposed adjacent to the first region, first conductive features embedded in the first region and separated by a first distance, a dielectric layer embedded in the ILD layer and disposed between the first conductive features in the first region, and second conductive features disposed in the second region and separated by a second distance greater than the first distance. The second region is free of the dielectric layer.

Methods of performing chemical-mechanical polishing process in semiconductor devices

The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

Integrated chip with graphene based interconnect

A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.

Titanium-containing diffusion barrier for CMP removal rate enhancement and contamination reduction

A semiconductor device includes a first underlying metal line and a second underlying metal line in a first dielectric layer over a substrate. The semiconductor device includes a first metal feature and a second metal feature in a second dielectric layer over the first dielectric layer. The first metal feature is over and connected to the first underlying metal line, and the second metal feature is over and connected to the second underlying metal line. The first metal feature has a first dimension, the second metal feature has a second dimension, the second dimension being greater than the first dimension. The first metal feature includes a first metal having a first mean free path, the second metal feature includes a second metal having a second mean free path, and the second mean free path is greater than the first mean free path.

Interconnect structures having varied materials

A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Graphene barrier layer for reduced contact resistance

Growing community of inventors

Hsinchu, Taiwan

Shau-Lin Shue