The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Jan. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Shao-Kuan Lee, Kaohsiung, TW;

Hai-Ching Chen, Hsinchu, TW;

Hsin-Yen Huang, New Taipei, TW;

Shau-Lin Shue, Hsinchu, TW;

Cheng-Chin Lee, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76829 (2013.01); H01L 21/76805 (2013.01); H01L 21/7682 (2013.01); H01L 21/76895 (2013.01); H01L 23/5329 (2013.01); H01L 23/535 (2013.01);
Abstract

An integrated chip includes a first metal line disposed over a substrate. A via is disposed directly over a top of the first metal line and the via has a first lower surface and a second lower surface above the first lower surface. A first dielectric structure is disposed laterally adjacent to the first metal line and along a sidewall of the first metal line. A first protective etch-stop structure is disposed directly over a top of the first dielectric structure and vertically separates the second lower surface of the via from the top of the first dielectric structure.


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