The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Feb. 07, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Cheng-Chin Lee, Hsinchu, TW;

Ting-Ya Lo, Hsinchu, TW;

Hsiao-Kang Chang, Hsinchu, TW;

Hsin-Yen Huang, Hsinchu, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10P 50/28 (2026.01); H10W 20/42 (2026.01); H10W 20/46 (2026.01); H10W 20/47 (2026.01);
U.S. Cl.
CPC ...
H10W 20/098 (2026.01); H10W 20/034 (2026.01); H10W 20/072 (2026.01); H10W 20/076 (2026.01); H10W 20/084 (2026.01); H10W 20/42 (2026.01); H10W 20/46 (2026.01); H10W 20/47 (2026.01); H10P 50/283 (2026.01); H10P 50/285 (2026.01); H10P 50/287 (2026.01); H10W 20/037 (2026.01); H10W 20/056 (2026.01); H10W 20/0888 (2026.01);
Abstract

An interconnection structure is provided. The interconnection structure includes an etching-process-free first dielectric layer, a first conductive structure extending within the first dielectric layer, a second dielectric layer formed under the first dielectric layer, and a second conductive structure extending through both the first dielectric layer and the second conductive layer.


Find Patent Forward Citations

Quick Actions:

Lee, Cheng-Chin. (2026). Semiconductor interconnection structures and methods of forming the same (U.S. Patent No. 12690436). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12690436

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