The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2021
Filed:
Oct. 21, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Ching-Fu Yeh, Hsinchu, TW;
Chao-Hsien Peng, Zhubei, TW;
Hsien-Chang Wu, Taichung, TW;
Hsiang-Huan Lee, Hsinchu County, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 21/76892 (2013.01); H01L 21/0271 (2013.01); H01L 21/0273 (2013.01); H01L 21/02115 (2013.01); H01L 21/02697 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H01L 21/76838 (2013.01); H01L 21/76885 (2013.01); H01L 21/76897 (2013.01); H01L 23/53276 (2013.01); B82Y 40/00 (2013.01); H01L 2221/1094 (2013.01); H01L 2924/0002 (2013.01); Y10S 977/742 (2013.01);
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.