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For the Inventor, By the Inventor

Hsinchu, Taiwan

Ching-Fu Yeh

This inventor holds 27 USPTO granted patents and 12 published patent applications, primarily in Semiconductor Fabrication. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Other. Active years: 2014-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ching-Fu Yeh. Retrieved from https://idiyas.com/inventor/ching-fu-yeh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 70.4

Average Co-Inventor Count = 3.8

ph-index = 4

Forward Citations = 45(Granted Patents)


Company Filing History:

goldMedal26 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal1 out of 834,513 
Other
 patents

Years Active: 2014-2026

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Areas of Expertise:
Barrier Layer Deposition
Vertical Conductive Graphene
Semiconductor Structure
Interconnect Structure
Aluminum Interconnection
Copper Interconnect
Integrated Circuit Fabrication
Graphene-Capped Metal
Via Plating
Back End of Line Processing
Salicide Production
Carbon Nanotube Contact
27 patents (USPTO):Explore Patents
1. 12660580 - Selective barrier layer deposition using blocking layers (2026-06-16),
2. 12648419 - Semiconductor structure having vertical conductive graphene and method for forming the same (2026-06-02),
3. 12027419 - Semiconductor device including liner structure (2024-07-02),
4. 11948837 - Semiconductor structure having vertical conductive graphene and method for forming the same (2024-04-02),
5. 10930552 - Method of semiconductor integrated circuit fabrication (2021-02-23),
6. 10651279 - Semiconductor interconnect structure having graphene-capped metal interconnects (2020-05-12),
7. 10453746 - Method of semiconductor integrated circuit fabrication (2019-10-22),
8. 10164018 - Semiconductor interconnect structure having graphene-capped metal interconnects (2018-12-25),
9. 10163698 - Interconnect structure and manufacturing method thereof (2018-12-25),
10. 9984975 - Barrier structure for copper interconnect (2018-05-29),
11. 9966339 - Barrier structure for copper interconnect (2018-05-08),
12. 9966304 - Method for forming interconnect structure (2018-05-08),
13. 9947583 - Method of semiconductor integrated circuit fabrication (2018-04-17),
14. 9640431 - Method for via plating with seed layer (2017-05-02),
15. 9613854 - Method and apparatus for back end of line semiconductor device processing (2017-04-04),

Title: Ching-Fu Yeh - Pioneering Female Inventor from Hsinchu

Introduction: Ching-Fu Yeh is a trailblazing inventor hailing from Hsinchu, Taiwan. She has made significant contributions to the field of technology and innovation, particularly in the realm of semiconductor devices.

Latest Patents: Ching-Fu Yeh holds several patents related to semiconductor manufacturing processes, including a groundbreaking method for enhancing the efficiency of silicon wafer production. Her innovative approaches have garnered attention and acclaim in the industry.

Career Highlights: With a career spanning over two decades, Ching-Fu Yeh has worked with leading technology companies in Taiwan, spearheading research and development projects that have pushed the boundaries of semiconductor technology. Her dedication to innovation and problem-solving has led to numerous breakthroughs in the field.

Collaborations: Throughout her career, Ching-Fu Yeh has collaborated with top researchers, engineers, and scientists in the semiconductor industry. Her ability to work effectively in multidisciplinary teams has been instrumental in the success of various projects and initiatives.

Conclusion: Ching-Fu Yeh's passion for innovation, coupled with her technical expertise, has established her as a prominent figure in the world of semiconductor technology. Her pioneering work continues to inspire the next generation of inventors and engineers, shaping the future of the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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