Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Ching-Fu Yeh

Hsiang-Huan Lee

Shin-Yi Yang

Ming-Han Lee

Chao-Hsien Peng

Hsien-Chang Wu

Shau-Lin Shue

Yu-Hung Lin

Chih-Wei Chang

Yu-Min Chang

Tz-Jun Kuo

Chen-Hua Douglas Yu

You-Hua Chou

Yu-Chen Chan

Ming Han Lee

Pei-Yin Liou

Sheng-Hsuan Lin

Shih-Chi Lin

Yao-Hsiang Liang

Shu-Wei Li

Meng-Pei Lu

Chin-Lung Chung

Guanyu Luo

Hsin-Chen Tsai

Andy Li

A semiconductor device includes an interconnect structure embedded in a first metallization layer comprising a dielectric material. The interconnect structure includes a first metal material. The semiconductor device includes a first liner structure embedded in the first metallization layer. The first liner structure is extended along one or more boundaries of the interconnect structure in the first metallization layer. The first liner structure includes a second metal material reacted with one or more dopants, the second metal material being different from the first metal material.

Semiconductor device including liner structure

A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Semiconductor structure having vertical conductive graphene and method for forming the same

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Method of semiconductor integrated circuit fabrication

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

Semiconductor interconnect structure having graphene-capped metal interconnects

A method for manufacturing a semiconductor comprises: providing a substrate; forming an opening in a dielectric layer disposed over the substrate; providing a target with a first type atoms; ionizing the first type atoms provided from the target; providing a bias to the substrate for controlling the moving paths of the ionized first type atoms thereby directing the ionized first type atoms in the opening; and forming a first conductive structure from bottom of the opening with the ionized first type atoms under a pre-determined frequency and a pre-determined pressure.

Interconnect structure and manufacturing method thereof

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.

A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.

Barrier structure for copper interconnect

An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an &#x3b1;-phase inducing metal layer is introduced on a first Ta barrier layer of &#x3b2; phase to induce the subsequent deposition of Ta thereon into the formation of an &#x3b1;-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of &#x3b1; phase has a lower Rc than that of the &#x3b2;-phase Ta barrier layer.

Method for forming interconnect structure

Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Method for via plating with seed layer

A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously.

Method and apparatus for back end of line semiconductor device processing

An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process.

Growing community of inventors

Hsinchu, Taiwan

Ching-Fu Yeh