The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Apr. 01, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Shin-Yi Yang, New Taipei, TW;

Hsi-Wen Tien, Hsinchu, TW;

Ming-Han Lee, Taipei, TW;

Hsiang-Huan Lee, Hsinchu County, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/28562 (2013.01); H01L 21/76816 (2013.01); H01L 21/76844 (2013.01); H01L 21/76876 (2013.01); H01L 21/76883 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 23/5226 (2013.01); H01L 23/53276 (2013.01); H01L 23/53295 (2013.01); H01L 21/28556 (2013.01); H01L 2221/1094 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.


Find Patent Forward Citations

Loading…