The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2017
Filed:
Jun. 09, 2014
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Ming-Han Lee, Taipei, TW;
Tz-Jun Kuo, Hsinchu, TW;
Chien-Hsin Ho, Taichung, TW;
Hsiang-Huan Lee, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/288 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76847 (2013.01); H01L 21/2885 (2013.01); H01L 21/76846 (2013.01); H01L 21/76861 (2013.01); H01L 21/76873 (2013.01); H01L 21/76879 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 2221/1063 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.