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For the Inventor, By the Inventor

Munich, Germany

Georg Meyer-Berg

This inventor holds 62 USPTO granted patents and 9 published patent applications, primarily in Semiconductor Devices (CPC class H01L). Top assignees: Infineon Technologies Ag, Intel Deutschland Gmbh, Infineon Technologies Austria Ag. Active years: 2002-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Georg Meyer-Berg. Retrieved from https://idiyas.com/inventor/georg-meyer-berg

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 62 

% Patents Active = 67.7

Average Co-Inventor Count = 2.0

ph-index = 6

Forward Citations = 189(Granted Patents)

Forward Citations (Not Self Cited) = 176(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Müchen, DE (2008)
  • Muenchen, DE (2012)
  • München, DE (2002 - 2018)
  • Munich, DE (2007 - 2023)

Company Filing History:

goldMedal55 out of 15,040 
 
Infineon Technologies Ag
 patents
silverMedal3 out of 254 
 
Intel Deutschland Gmbh
 patents
bronzeMedal2 out of 2,211 
 
Infineon Technologies Austria Ag
 patents
4. 2 out of 56,394 
 
Intel Corporation
 patents

Years Active: 2002-2024

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Areas of Expertise:
Semiconductor Device
Power Module
Chip Package
Integrated Circuit
Die Attach
Passive Component
Thermoplastic Dielectric
Battery State Detection
62 patents (USPTO):Explore Patents
1. 12154878 - Semiconductor device (2024-11-26),
2. 11848294 - Semiconductor device (2023-12-19),
3. 11322451 - Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module (2022-05-03),
4. 11233027 - Semiconductor device (2022-01-25),
5. 11195787 - Semiconductor device including an antenna (2021-12-07),
6. 10854547 - Chip package with cross-linked thermoplastic dielectric (2020-12-01),
7. 10734352 - Metallic interconnect, a method of manufacturing a metallic interconnect, a semiconductor arrangement and a method of manufacturing a semiconductor arrangement (2020-08-04),
8. 10679959 - Semiconductor device (2020-06-09),
9. 10600690 - Method for handling a product substrate and a bonded substrate system (2020-03-24),
10. 10529678 - Semiconductor device (2020-01-07),
11. 10522447 - Chip package and a wafer level package (2019-12-31),
12. 10297564 - Semiconductor die attach system and method (2019-05-21),
13. 10211158 - Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module (2019-02-19),
14. 10177112 - Attaching chip attach medium to already encapsulated electronic chip (2019-01-08),
15. 10121690 - Method of manufacturing a semiconductor component and semiconductor component (2018-11-06),

Title: The Innovative Mind of Georg Meyer-Berg

Introduction: Georg Meyer-Berg, a distinguished inventor hailing from Munich, Germany, has made significant contributions to the world of technology and innovation.

Latest Patents: Georg Meyer-Berg's latest patents focus on renewable energy solutions, with a particular emphasis on solar power optimization and energy storage technologies.

Career Highlights: With a career spanning over two decades, Georg Meyer-Berg has been at the forefront of cutting-edge technological advancements. His work has revolutionized the way we harness and utilize renewable energy sources.

Collaborations: Throughout his career, Georg Meyer-Berg has collaborated with leading research institutions and universities to further his innovative projects. His partnerships have led to groundbreaking developments in the field of sustainable energy.

Conclusion: Georg Meyer-Berg's passion for innovation and commitment to sustainability have solidified his position as a visionary inventor in the realm of renewable energy technologies. His contributions continue to shape the future of clean energy solutions worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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