The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Dec. 23, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Georg Meyer-Berg, München, DE;

Edward Fuergut, Dasing, DE;

Joachim Mahler, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/94 (2013.01);
Abstract

Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.


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