Infineon Technologies Ag

Intel Deutschland Gmbh

Intel Corporation

Infineon Technologies Austria Ag

Georg Meyer-Berg

Joachim Mahler

Khalil Hosseini

Edward Fuergut

Horst Theuss

Klaus Elian

Christoph Kutter

Reinhard Pufall

Ewald Soutschek

Juergen Hoegerl

Dominic Maier

Frank Daeche

Michael Bauer

Gottfried Beer

Olaf Hohlfeld

Daniel Porwol

Tobias Schmidt

Magdalena Hoier

Andreas Schloegl

Holger Doepke

Claus Von Waechter

Michael Goroll

Rainer Dudek

Ralf Otremba

Thorsten Meyer

Saverio Trotta

Josef Hoeglauer

Ivan Nikitin

Ashutosh Baheti

Guenther Ruhl

Manfred Schneegans

Jochen Dangelmaier

Irmgard Escher-Poeppel

Maciej Wojnowski

Edmund Riedl

Mathias Vaupel

Thomas Kilger

Barbara Vasquez

Manfred Fries

Rainer Steiner

Thomas Mueller

Johannes Lodermeyer

Claus Waechter

Frank Kahlmann

Ngoc-Hoa Huynh

Franz-Xaver Muehlbauer

Christian Birzer

Klaus Schmidt

Guenter Tutsch

Patrick Schwarz

Veronika Huber

A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Semiconductor device

A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module

A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

Semiconductor device including an antenna

A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.

Chip package with cross-linked thermoplastic dielectric

A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

Metallic interconnect, a method of manufacturing a metallic interconnect, a semiconductor arrangement and a method of manufacturing a semiconductor arrangement

A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.

Method for handling a product substrate and a bonded substrate system

Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

Chip package and a wafer level package

A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.

Semiconductor die attach system and method

A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

Attaching chip attach medium to already encapsulated electronic chip

Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.

Method of manufacturing a semiconductor component and semiconductor component

Growing community of inventors

Munich, Germany

Georg Meyer-Berg