Chih-Liang Chen

USPTO Granted Patents = 196 (Patent Applications = 59)

EPO Patents = 1 (Patent Applications = 1)

Average Co-Inventor Count = 5.1

ph-index = 8

Forward Citations = 379(Granted Patents)

Forward Citations (Not Self Cited) = 312(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Taipei, TW (2006 - 2021)
Hinchu, TW (2023)
Hsinchu, TW (2014 - 2024)

Company Filing History:

193 out of 40,674

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

5 out of 114

TSMC China Company Limited

patents

2 out of 3,599

Macronix International Co., Ltd.

TSMC Nanjing Company, Limited

patents

where one patent can have more than one assignee

Years Active: 2006-2025

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Areas of Expertise:

Semiconductor Manufacturing

Integrated Circuits

Flip-Flop Design

Transistor Structures

Electrostatic Discharge Protection

3D Integrated Circuits

Power Rail Arrangement

Buried Conductive Structures

Self-Aligned Interconnects

Finfet Devices

Metal Patterning

V2V Rail Technology

196 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12477790 - Method of manufacturing semiconductor structure (2025-11-18),

2. 12471377 - Method of forming semiconductor device having segmented interconnect (2025-11-11),

3. 12469786 - Integrated circuit and method for forming the same (2025-11-11),

4. 12450417 - Semiconductor metal layer structure over cell region (2025-10-21),

5. 12444684 - Semiconductor device including parallel configuration (2025-10-14),

6. 12419114 - Integrated circuit (2025-09-16),

7. 12417980 - First metal structure, layout, and method (2025-09-16),

8. 12408440 - Method of making amphi-FET structure and method of designing (2025-09-02),

9. 12401348 - Footprint for multi-bit flip flop (2025-08-26),

10. 12395157 - Footprint for multi-bit flip flop (2025-08-19),

11. 12382724 - Layout design for header cell in 3D integrated circuits (2025-08-05),

12. 12381148 - Buried pad for use with gate-all-around device (2025-08-05),

13. 12381145 - Signal conducting line arrangements in integrated circuits (2025-08-05),

14. 12364006 - Integrated circuit and method of forming same (2025-07-15),

15. 12346644 - Arrangement of source or drain conductors of transistor (2025-07-01),

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59 patents pending:

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1 patent (EPO):

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1 patent pending (EPO):

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