Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

Macronix International Co., Ltd.

Aopen Incorporated

TSMC Nanjing Company, Limited

Comp-any Gmbh

Chih-Liang Chen

Charles Chew-Yuen Young

Jiann-Tyng Tzeng

Hui-Zhong Zhuang

Kam-Tou Sio

Chih-Ming Lai

Ru-Gun Liu

Li-Chun Tien

Wei-Cheng Lin

Guo-Huei Wu

Shih-Wei Peng

Hui-Ting Yang

Lei-Chun Chou

Chun-Kuang Chen

Chi-Yu Lu

Shun Li Chen

Chih-Yu Lai

Cheng-Chi Chuang

Chia-Tien Wu

Jung-Chan Yang

Ching-Wei Tsai

Shang-Wen Chang

Pochun Wang

Meng-Hung Shen

Po-Chun Wang

Tzu-Chiang Chen

Shi Ning Ju

Hung-Li Chiang

Kuo-Nan Yang

I-Sheng Chen

Yung-Sung Yen

Yi-Hsun Chiu

Wei-Liang Lin

Chin-Yuan Tseng

Chi-Yeh Yu

Chew-Yuen Young

Kuo-Cheng Ching

Lee-Chung Lu

Wen-Hao Chen

Ting Yu Chen

Shun-Li Chen

Kuang-Ching Chang

Shang-Hsuan Chiu

Chih-Hao Wang

Jack Liu

Shang-Syuan Ciou

Shu-Hui Sung

Chun-Hung Liou

Chao-Ching Cheng

Tien-Lu Lin

Ta-Pen Guo

Fong-yuan Chang

Wei-Hao Wu

Jerry Chang Jui Kao

Yu-Lin Yang

Ko-Bin Kao

Szu-Wei Huang

Ho Che Yu

Wei-Ling Chang

Jian-Sing Li

Xin-Yong Wang

Kam-tou Sio

Chia-Hao Chang

Xiangdong Chen

Po-Hsiang Huang

Pin-Dai Sue

Jerry Chang-Jui Kao

Yi-Hsiung Lin

Hsin-Chih Chen

Tzu-Ying Lin

Shao-Lun Chien

Wei-Chen Chien

Kuo-Cheng Chiang

Ting-Wei Chiang

Tsong-Hua Ou

Tzu-Heng Chang

Wei-An Lai

Cheng-I Huang

Ching-Fang Huang

XinYong Wang

Sing-Kai Huang

Cheng-Yu Lin

Yen-Ming Chen

Chung-Hsing Wang

Jaw-Juinn Horng

Sheng-Hsiung Chen

Chia-Chung Chen

Yuan-Te Hou

Shang-Chih Hsieh

Chin-Shen Lin

Fong-Yuan Chang

Szu-Lin Liu

Wan-Yu Lo

Tsung-Yao Wen

Jui-Yao Lai

Ya Yun Liu

Yi-Feng Chen

Jung-chan Yang

Wei-Ren Chen

Metallization structure for an integrated circuit. In one embodiment, an integrated circuit includes a metal-to-diffusion (MD) layer disposed over an active region of a cell, gates disposed over the active region of the cell, and a first metallization layer including M0 tracks disposed over the MD layer and the gates. The integrated circuit further includes a second metallization layer including M1 tracks disposed over the first metallization layer. The M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, wherein the first M1 tracks are longer than the second M1 tracks.

Semiconductor metal layer structure over cell region

A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.

Semiconductor device including parallel configuration

An integrated circuit (IC) structure includes two active areas extending in a first direction, two gate structures extending in a second direction, a first metal segment extending in the second direction in a first metal layer, second and third metal segments extending in the first direction in a second metal layer, and a gate via structure extending from the third metal segment to one of the gate structures. The gate structures overlie the active areas, the first metal segment overlies each of the active areas between the gate structures, the second metal segment overlies a first active area and overlies and is electrically connected to the first metal segment, and the first and second metal segments are electrically connected to the second active area, isolated from the first active area between the gate structures, and connected to the first active area outside the gate structures.

First metal structure, layout, and method

An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.

Integrated circuit

A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Method of making amphi-FET structure and method of designing

An integrated circuit provided here includes a N-bit flip-flop and a first clock cell. The N-bit flip-flop includes first cell of a first bit and a second cell of a second bit. An output signal from the first cell is inputted into the second cell in response to a first clock signal. The first and second cells have different widths and are arranged in a first row of multiple first cell rows and a first row of multiple second cell rows respectively. The first cell rows and the second cell rows have different row heights. The first clock cell outputs the first clock signal and is arranged in the first row of the second cell rows to abut the first cell.

Footprint for multi-bit flip flop

An integrated circuit includes first bit cells, second bit cells, and clock cells. Each of first bit cells is arranged in one of multiple first cell rows having a first row height. Each of the second bit cells is arranged in one of multiple second cells rows having a second row height different from the first row height. The second bit cells extend to pass the first bit cells in a first direction. The clock cells are arranged in peripheral regions of a multi-bit flip flop cell in the first cell rows. The first and second bit cells and the clock cells are included in the multi-bit flip flop cell.

A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.

Buried pad for use with gate-all-around device

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Layout design for header cell in 3D integrated circuits

A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

Signal conducting line arrangements in integrated circuits

An integrated circuit includes a set of transistors including a set of active regions, a set of power rails, a first set of conductors and a first conductor. The set of active regions extends in a first direction, and is on a first level. The set of power rails extends in the first direction and is on a second level. The set of power rails has a first width. The first set of conductors extends in the first direction, is on the second level, and overlaps the set of active regions. The first set of conductors has a second width. The first conductor extends in the first direction, is on the second level and is between the first set of conductors. The first conductor has the first width, electrically couples a first transistor of the set of transistors to a second transistor of the set of transistors.

Integrated circuit and method of forming same

An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. A distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

Arrangement of source or drain conductors of transistor

A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Metal patterning for internal cell routing

A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Semiconductor device including source/drain contact having height below gate stack

A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

Power rail and signal conducting line arrangement

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Hsinchu, Taiwan

Chih-Liang Chen