The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Apr. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chun-Chi Tsai, Hsinchu, TW;

Jung-Chan Yang, Taoyuan County, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Chih-Liang Chen, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/392 (2020.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/392 (2020.01); H10D 84/017 (2025.01); H10D 84/0179 (2025.01); H10D 84/0186 (2025.01); H10D 84/0191 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for semiconductor manufacturing is provided. The method includes defining a first cell level group comprising a first set of pattern features corresponding to a predetermined manufacturing process associated with an layout; determining a first number of cell units based on the first cell level group, wherein each of the first number of cell units is compatible with each other; defining a second cell level group comprising the first set of pattern features and a second set of pattern features; and determining a second number of cell units based on the second cell level group, wherein each of the second number of cell units is compatible with each other. The first set of pattern features and the second set of pattern features are arranged in responsive to sequential operations of the predetermined manufacturing process.


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