Austin, TX, United States of America

Charles Jay Alpert

This inventor holds 128 USPTO granted patents and 4 published patent applications, primarily in Clock Tree Synthesis (CPC class G06F17-5077). Top assignees: International Business Machines Corporation, Cadence Design Systems, Inc., Globalfoundries Inc.. Active years: 2000-2026.

USPTO Granted Patents = 128 

% Patents Active = 55.5

Average Co-Inventor Count = 4.2

ph-index = 14

Forward Citations = 1,200(Granted Patents)

Forward Citations (Not Self Cited) = 1,082(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Pflugerville, TX (US) (2000)
  • Round Rock, TX (US) (2004 - 2010)
  • Austin, TX (US) (2002 - 2022)
  • Cedar Park, TX (US) (2008 - 2024)

Company Filing History:


Years Active: 2000-2026

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Areas of Expertise:
Clock Tree Synthesis
Routing Optimization
Layer Assignment
Power-Driven Synthesis
Pin Density Adjustment
Timing Modeling
Buffering Solutions
Cell Placement
Circuit Design
Fault-Tolerant Synthesis
Network Assignment
Hierarchical Buffering
128 patents (USPTO):Explore Patents

Title: Innovations and Contributions of Charles Jay Alpert

Introduction

Charles Jay Alpert, based in Austin, TX, is a prolific inventor with an impressive portfolio of 112 patents. His work has significantly impacted the fields of integrated circuit design and neurosynaptic networks, showcasing his innovative approach to problem-solving within the technology sector.

Latest Patents

Alpert's latest patents demonstrate his ingenuity in enhancing integrated circuit designs and power efficiency. One notable patent, titled "Post-CTS insertion delay and skew target reformulation of clock tree," introduces methods and systems for optimizing clock trees in integrated circuits. This invention facilitates the analysis and adjustment of insertion delays associated with clock sinks, streamlining performance and reducing skew thresholds.

Another significant contribution is the patent for "Fault-tolerant power-driven synthesis," which aims to minimize power consumption in multi-core neurosynaptic networks. This method involves identifying faulty cores within a network and optimizing the placement of neurosynaptic cores to decrease wire length, ultimately achieving fault tolerance and efficient power usage.

Career Highlights

Throughout his career, Alpert has worked with esteemed organizations like IBM and Cadence Design Systems, Inc., where he has contributed to various advancements in technology. His experience in these companies has equipped him with the knowledge and expertise necessary to drive innovation and implement effective solutions in complex engineering problems.

Collaborations

Alpert has collaborated with several notable professionals in the field, including Zhuo Li and Chin Ngai Sze. These partnerships have fostered a dynamic exchange of ideas and techniques, further enhancing the quality of the innovations he has developed.

Conclusion

Charles Jay Alpert's contributions to the realms of integrated circuit design and neurosynaptic networks underscore his role as a pioneering inventor. With a substantial number of patents to his name, his work continues to influence future developments and innovations in technology.

Profile summary based on public USPTO records.
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