The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Feb. 06, 2023
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Amin Farshidi, Austin, TX (US);
Zhuo Li, Austin, TX (US);
Michael Alexander, Graham, WA (US);
Charles Jay Alpert, Cedar Park, TX (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/06 (2006.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); G06F 30/3312 (2020.01);
U.S. Cl.
CPC ...
G06F 1/06 (2013.01); G06F 30/396 (2020.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01);
Abstract
Various embodiments provide for cloning a clock gate based on input/output switching activity of clocked circuit elements gated by the clock gate, where the cloning can be performed as part of a clock tree generation or optimization process performed by an electronic design automation (EDA) software.