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For the Inventor, By the Inventor

San Jose, CA, United States of America

Cadence Design Systems, Inc.


USPTO Granted Patents = 2,546



Trademarks = 50

Forward Citations = 26,317

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2,323 inventors (with patents filed for the assignee):

goldMedal Steven L Teig (155 out of 447 patents)

silverMedal Zhuo Li (67 out of 123 patents)

bronzeMedal Arnold Ginetti (58 out of 72 patents)

4.  Vivek Chickermane (56 out of 56 patents)

5.  Mitchell Grant Poplack (56 out of 65 patents)

6.  Andrew Edward Caldwell (54 out of 113 patents)

7.  David Allan White (45 out of 89 patents)

8.  Donald John O'Riordan (44 out of 44 patents)

9.  Igor Keller (41 out of 42 patents)

10.  Taranjit Singh Kukal (35 out of 35 patents)

11.  Eric Harris Naviasky (33 out of 36 patents)

12.  Louis K Scheffer (33 out of 33 patents)

13.  Joel Reuben Phillips (30 out of 30 patents)

14.  Hongzhou Liu (29 out of 29 patents)

15.  Krishna Chakravadhanula (29 out of 29 patents)


Core Competencies:
Circuit Design
Formal Verification
Power Consumption
Clock Tree Synthesis
Electromagnetic Modeling
Integrated Circuit Design
Machine Learning
High-Speed Systems
Signal Processing
User Interface
Timing Analysis
Fault Detection

2,546 patents:

1. 12511462 - Physical awareness of test-point sharing in a circuit design (2025-12-30),
2. 12505277 - Cell-based pin access location generation (2025-12-23),
3. 12505276 - Method and system to facilitate schematics for an electronic design (2025-12-23),
4. 12505274 - Detecting and modeling via during global routing (2025-12-23),
5. 12488176 - Systems and methods for reducing test point power consumption in a circuit design (2025-12-02),
6. 12487905 - User interface for formal verification of computer instructions for compatibility with a compiler architecture (2025-12-02),
7. 12483248 - LFPS pulse detection using unit interval adjustment based on average pulse width (2025-11-25),
8. 12481811 - Circuit design modification based on timing tradeoff (2025-11-25),
9. 12476653 - Methods and circuits for inner-eye timing center detection and clock phase alignment (2025-11-18),
10. 12476626 - System and method for skew-tolerant, glitch-free multiplexing with auto-strobe burst detection (2025-11-18),
11. 12475288 - Clock-based test-point flop sharing in a circuit design (2025-11-18),
12. 12475286 - System and method for comparing circuit design constraint sets (2025-11-18),
13. 12475282 - Cross-querying between distributed interactive applications (2025-11-18),
14. 12468875 - Method and system to implement altitude based I/O re-layering for electronic and photonic designs (2025-11-11),
15. 12461748 - Method and apparatus for encoding of processor instruction set (2025-11-04),
Cadence Design Systems, Inc. is an American electronic design automation (EDA) software and engineering services company. It provides software, hardware, and intellectual property (IP) for designing integrated circuits (ICs), printed circuit boards (PCBs), and systems-on-chips (SoCs). Cadence's products are used in various industries including automotive, aerospace and defense, consumer electronics, and more. The company is headquartered in San Jose, California, and has offices worldwide.
This text is generated by artificial intelligence and may not be accurate.

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USPTO Data Jan 1 1976 - Dec 30 2025

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2,546 Patents

#11 in San Jose, CA

#45 in California

#178 in US

#365 in the World

...
San Jose, CA, United States of America

Cadence Design Systems, Inc.

Forward Citations = 26,317

2,323 inventors:

goldMedal Steven L Teig (155 out of 447 patents)

silverMedal Zhuo Li (67 out of 123 patents)

bronzeMedal Arnold Ginetti (58 out of 72 patents)

4.  Vivek Chickermane (56 out of 56 patents)

5.  Mitchell Grant Poplack (56 out of 65 patents)

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