The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Sep. 27, 2022
Cadence Design Systems, Inc., San Jose, CA (US);
Brian Foutz, Charlottesville, VA (US);
Krishna Chakravadhanula, Vestal, NY (US);
Prateek Kumar Rai, Uttar Pradesh, IN;
Sarthak Singhal, Noida—UttarPradesh, IN;
Vivek Chickermane, Slaterville Springs, NY (US);
Huafeng Yang, San Jose, CA (US);
Christos Papameletis, Apex, NC (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A system includes a memory that stores instructions and a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a circuit layout module that generates an initial circuit layout in response to a circuit netlist. The circuit netlist includes functional logic, the test-point nodes interconnecting portions of the functional logic, and a plurality of test-point flops associated with scan-chains. The EDA application also includes a test-point flop allocation module that divides the test-point nodes into test-point sharing groups based on a physical location of the test-point nodes and based on a test-point allocation parameter. The module relocates each of the test-point flops proximal to a test-point sharing group to generate an adjusted circuit layout associated with the circuit design. The adjusted circuit layout is employable to fabricate an integrated circuit (IC) chip.