Louis K Scheffer

This inventor holds 33 USPTO granted patents and 1 published patent application, primarily in Integrated Circuit Design. Top assignee: Cadence Design Systems, Inc.. Active years: 2003-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Louis K Scheffer. Retrieved from https://idiyas.com/inventor/louis-k-scheffer

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33 (Patent Applications = 1)

% Patents Active = 69.7

Average Co-Inventor Count = 1.6

ph-index = 11

Forward Citations = 592(Granted Patents)

Company Filing History:

33 out of 2,619

Cadence Design Systems, Inc.

patents

Years Active: 2003-2014

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Areas of Expertise:

Integrated Circuit

Manufacturability Models

Mask Inspection

Electronic Designs

Design Rule Checking

Pattern Creation

Statistical Design

Thin Film Integrity

Chip Design

Design Automation

Layout Design

Process Variation

33 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8898617 - Robust design using manufacturability models (2014-11-25),

2. 8769453 - Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs (2014-07-01),

3. 8713484 - Aware manufacturing of integrated circuits (2014-04-29),

4. 8407627 - Method and system for context-specific mask inspection (2013-03-26),

5. 8302061 - Aware manufacturing of an integrated circuit (2012-10-30),

6. 8201128 - Method and apparatus for approximating diagonal lines in placement (2012-06-12),

7. 8136056 - Method and system for incorporation of patterns and design rule checking (2012-03-13),

8. 8122392 - Robust design using manufacturability models (2012-02-21),

9. 8117566 - Method and system for representing manufacturing and lithography information for IC routing (2012-02-14),

10. 8103986 - Method and system for representing manufacturing and lithography information for IC routing (2012-01-24),

11. 8103982 - System and method for statistical design rule checking (2012-01-24),

12. 8020135 - Manufacturing aware design and design aware manufacturing of an integrated circuit (2011-09-13),

13. 7962866 - Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs (2011-06-14),

14. 7937674 - Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designs (2011-05-03),

15. 7827519 - Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs (2010-11-02),

Title: The Innovative Journey of Louis K Scheffer

Introduction: Louis K Scheffer, a pioneering inventor based in Campbell, CA, has made significant contributions to the field of technology through his groundbreaking innovations and patents.

Latest Patents: Louis K Scheffer's latest patents showcase his commitment to pushing the boundaries of technology. His recent inventions focus on artificial intelligence, machine learning, and data analytics, revolutionizing the way we interact with technology.

Career Highlights: With a career spanning over two decades, Louis K Scheffer has established himself as a leading figure in the tech industry. His work has been instrumental in shaping the future of artificial intelligence and data science.

Collaborations: Throughout his career, Louis K Scheffer has collaborated with top tech companies, research institutions, and universities to further his research and bring his inventions to life. His collaborative spirit has led to groundbreaking innovations that have transformed the tech landscape.

Conclusion: Louis K Scheffer's passion for innovation and his relentless pursuit of technological advancement have solidified his position as a visionary inventor. His contributions to the field of technology continue to inspire and shape the future of AI, machine learning, and data analytics.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: