The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
May. 19, 2006
Louis K. Scheffer, Campbell, CA (US);
David C. Noice, Palo Alto, CA (US);
Louis K. Scheffer, Campbell, CA (US);
David C. Noice, Palo Alto, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes 'known good' patterns, which chip fabricators know from experience are successful, and 'known bad' patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.