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For the Inventor, By the Inventor

Pleasanton, CA, United States of America

Igor Keller

USPTO Granted Patents = 42 

Average Co-Inventor Count = 2.8

ph-index = 12

Forward Citations = 801(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (2008 - 2011)
  • Pleasanton, IL (US) (2013)
  • Pleasanton, CA (US) (2008 - 2024)

Company Filing History:

goldMedal41 out of 2,542 
 
Cadence Design Systems, Inc.
 patents
silverMedal1 out of 832,680 
Other
 patents

Years Active: 2008-2024

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42 patents (USPTO):Explore Patents
1. 12086529 - Circuit design modification using timing-based yield calculation (2024-09-10),
2. 11775719 - Cell instance charge model for delay calculation (2023-10-03),
3. 11188696 - Method, system, and product for deferred merge based method for graph based analysis pessimism reduction (2021-11-30),
4. 11023640 - Methods, systems, and computer program product for characterizing timing behavior of an electronic design with a derived current waveform (2021-06-01),
5. 11023636 - Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window (2021-06-01),
6. 10963610 - Analyzing clock jitter using delay calculation engine (2021-03-30),
7. 10789406 - Characterizing electronic component parameters including on-chip variations and moments (2020-09-29),
8. 10430536 - Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation (2019-10-01),
9. 10275554 - Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design (2019-04-30),
10. 10192012 - Pseudo-inverter configuration for signal electromigration analysis (2019-01-29),
11. 10185795 - Systems and methods for statistical static timing analysis (2019-01-22),
12. 10073934 - Systems and methods for statistical static timing analysis (2018-09-11),
13. 9928324 - System and method for accurate modeling of back-miller effect in timing analysis of digital circuits (2018-03-27),
14. 9881123 - Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact (2018-01-30),
15. 9710593 - Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs (2017-07-18),

Title: A Glimpse into the Innovations of Inventor Igor Keller

Introduction:

Inventor Igor Keller, based in Pleasanton, CA, is a visionary mind with a remarkable track record in the field of technology and circuit design. With 41 patents to his name, Keller has significantly contributed to advancements in electronic design automation (EDA) and graph-based analysis.

Latest Patents:

Among his latest patents is the 'Cell Instance Charge Model for Delay Calculation', a groundbreaking invention that enhances timing analysis of circuit designs by predicting charges at cell instances and mitigating time delay impacts. Another notable patent is the 'Deferred Merge Based Method for Graph-Based Analysis Pessimism Reduction', which optimizes worst-case timing analysis by deferring signal mergers based on specific conditions.

Career Highlights:

Keller has made significant strides in his career, notably working at Cadence Design Systems, Inc., a prominent player in the EDA industry. His expertise and innovative solutions have earned him recognition as a thought leader in circuit design and timing analysis.

Collaborations:

Throughout his career, Keller has collaborated with industry experts such as Joel Reuben Phillips and Vinod Kariat. These collaborations have led to the development of cutting-edge technologies and solutions that have reshaped the landscape of EDA and timing analysis.

Conclusion:

In conclusion, Igor Keller's innovative spirit and dedication to technological advancements have solidified his position as a pioneer in the field of circuit design. His patents and collaborations stand as a testament to his commitment to pushing the boundaries of innovation and shaping the future of technology.

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