The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2020
Filed:
Nov. 16, 2018
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/30 (2020.01); G06F 30/367 (2020.01); G06F 30/3312 (2020.01); G06F 111/04 (2020.01); G06F 111/10 (2020.01); G06F 111/20 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/30 (2020.01); G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 2111/04 (2020.01); G06F 2111/10 (2020.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01);
Abstract
The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly accurate extraction of electronic component timing parameters including on-chip variation information such as sigma and moments.