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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10963610 B1

PDFFull Text
Date of Patent:
Mar. 30, 2021

Filed:

May. 22, 2020

Analyzing clock jitter using delay calculation engine

Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Igor Keller, Pleasanton, CA (US);

Vishnu Kumar, Noida, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:

Foley & Lardner LLP

Primary Examiner:

Phallaka Kik

Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/3315 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01); G06F 30/398 (2020.01); G06F 30/367 (2020.01); G06F 30/3312 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

The present embodiments are generally directed to analyzing clock jitter. Jitter affects the clock delay of the circuit and the time the clock is available at sync points, so it is important to calculate its impact correctly to take appropriate margin during timing analysis. Jitter could be due to various reasons—one of them is due to IR Impact on the Clock Tree. IR drop variations between the two consecutive cycles can effectively reduce the available clock period for data to be correctly captured.

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Quick Actions:

Keller, Igor. (2021). Analyzing clock jitter using delay calculation engine (U.S. Patent No. 10963610). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10963610

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