Cadence Design Systems, Inc.

Other

Igor Keller

Joel Reuben Phillips

Vinod Kariat

King Ho Tam

Jijun Chen

Saurabh Kumar Tiwary

Praveen Ghanta

Manuj Verma

Mikhail Chetin

Eddy Pramono

Pradeep Yadav

Ratnakar Goyal

Shiva Raja

Arun Kumar Mishra

Ling Wang

Sharad Mehrotra

Naresh Kumar

Krishna Prasad Belkhale

Amit Dhuria

Arvind Nembili Veeravalli

Pawan Kulshreshtha

Xiaopeng Dong

Yang Gao

Nishath Verghese

Jalal Wehbeh

Ajish Thomas

Lizheng Zhang

Kenneth Tseng

Federico Politi

Aswin Ramakrishnan

Xiaoliang Bai

Nikolay Rubanov

Sneh Saurabh

Vishnu Kumar

Dhananjay Kumar Griyage

Joel R Philips

Qunzeng Liu

Venkat Thanvantri

Sourabh Rajguru

Harmandeep Singh

Eric K Anderson

Chirayu S Amin

Jean Pierre Hiol

Omid Assare

Sri Harsha Venkata Pothukuchi

William Franson Scott

Xiaojun Sun

Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.

Circuit design modification using timing-based yield calculation

Various embodiments provide a charge model for a cell instance for delay calculation of a circuit design that includes the cell instance, where the charge model can be part of electronic design automation (EDA) and used in timing analysis of a circuit design that includes the cell instance. The charge model generated by an embodiment can predict a charge at an input of a cell instance for an arbitrary input voltage waveform and can address (e.g., reduce or negate) a time delay impact the Miller effect has on the cell instance.

Cell instance charge model for delay calculation

An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.

Method, system, and product for deferred merge based method for graph based analysis pessimism reduction

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.

Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window

Disclosed are methods, systems, and articles of manufacture for characterizing timing behavior of an electronic design with a derived current waveform. A set of inputs is determined from a set of electrical characteristics of an electronic design or a portion thereof. Moreover, A derived current waveform is determined at one or more modules stored in memory and executing in conjunction with a microprocessor of a computing node based at least in part upon the set of inputs. The electronic design or the portion thereof is characterized based at least in part upon the derived current waveform.

Methods, systems, and computer program product for characterizing timing behavior of an electronic design with a derived current waveform

The present embodiments are generally directed to analyzing clock jitter. Jitter affects the clock delay of the circuit and the time the clock is available at sync points, so it is important to calculate its impact correctly to take appropriate margin during timing analysis. Jitter could be due to various reasons&#x2014;one of them is due to IR Impact on the Clock Tree. IR drop variations between the two consecutive cycles can effectively reduce the available clock period for data to be correctly captured.

Analyzing clock jitter using delay calculation engine

The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly accurate extraction of electronic component timing parameters including on-chip variation information such as sigma and moments.

Characterizing electronic component parameters including on-chip variations and moments

An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common segments of different paths are analyzed using shared data and where subsequent stages are transformed to provide an expected correlation between stages, and generating yield probability results based on at least the results of calculating timing analysis.

Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation

A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining a partial derivative of a delay function relative to the input slew rate, determining a delay distribution for a signal through a plurality of logic stages using the correlation value, the coskewness value, and the partial derivative of the delay function relative to the input slew rate. The method also includes verifying that a statistical value of the delay distribution satisfies a desired performance value for an integrated circuit.

Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design

A method for determining a signal electromigration effect in a circuit includes obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a complementary netlist that couples a second input with the output is provided. The complementary netlist is logically independent from the reference netlist. The method includes modifying the partition netlist to couple the reference netlist and the complementary netlist in an inverting configuration, and providing an electromagnetic pulse to at least one of the first input or the second input to induce a current through one of the plurality of circuit components. The method also includes determining an electromigration effect from the current on the one of the plurality of circuit components.

Pseudo-inverter configuration for signal electromigration analysis

Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

Systems and methods for statistical static timing analysis

Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is then accessed in other embodiments, and scaled to generate scaled timing values describing the statistical timing characteristics of a circuit element or block estimated from the skew-based values. These values may then be used for further timing analysis.

A system, method, and computer program product for modeling a receiver load in static timing analysis of digital circuits. Embodiments separate total receiver charge into static and dynamic components, and extract both from an improved library model. The receiver load is effectively modeled with a static capacitance and a current source connected in parallel. A method of extracting load model characteristics from a standard timing library is also provided. The improved receiver model reflects the physical phenomena not currently modeled, and enables a more accurate description of circuit behavior while still using a simple approximation of the transistor level circuit. The complete circuit switching response is found through a perturbative approach, combining a linear response using constant capacitance values with a correction having time-dependent charges for modeling physical phenomena such as the back-Miller effect. The result is improved circuit timing evaluation, with good accuracy versus SPICE simulation for waveforms and delays.

System and method for accurate modeling of back-miller effect in timing analysis of digital circuits

A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.

Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact

Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.

Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs

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Pleasanton, CA, United States of America

Igor Keller