The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2021
Filed:
Apr. 15, 2019
Cadence Design Systems, Inc., San Jose, CA (US);
Amit Dhuria, Fremont, CA (US);
Sri Harsha Venkata Pothukuchi, San Jose, CA (US);
Pradeep Yadav, Uttar Pradesh, IN;
Pawan Kulshreshtha, San Jose, CA (US);
Igor Keller, Pleasanton, CA (US);
Sharad Mehrotra, Cedar Park, TX (US);
Jean Pierre Hiol, San Jose, CA (US);
Krishna Prasad Belkhale, Saratoga, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.