The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2025
Filed:
Jan. 11, 2022
Cadence Design Systems, Inc., San Jose, CA (US);
Jagjot Kaur, Fremont, CA (US);
Vivek Chickermane, Slaterville Springs, NY (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to reducing power consumption of test point circuit elements of an integrated circuit (IC) design. An ungated input clock for at least one testing point circuit element for the IC design can be identified. The IC design can be updated by coupling a test point clock gating circuit element to a clock gate input node of the IC design that is to receive the ungated input clock, to the at least one test point circuit element, and to a test mode signal generation element that is to provide a test mode signal to create an updated IC design. The test point clock gating circuit element can be enabled and disabled based on a logical value of the test mode signal to control a supply of the ungated input clock to the at least one testing point circuit element.