The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Sep. 27, 2022
Cadence Design Systems, Inc., San Jose, CA (US);
Brian Foutz, Charlottesville, VA (US);
Vivek Chickermane, Slaterville Springs, NY (US);
Bharath Nandakumar, New Delhi, IN;
Sameer Chakravarthy Chillarige, Bengaluru, IN;
Krishna Chakravadhanula, Vestal, NY (US);
Prateek Kumar Rai, Uttar Pradesh, IN;
Sarthak Singhal, Noida-Uttar Pradesh, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.