The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2025
Filed:
Feb. 06, 2023
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Mateus Paiva Fogaça, Porto Alegre, BR;
Gracieli Posser, Austin, TX (US);
Mehmet Can Yildiz, Austin, TX (US);
Charles Jay Alpert, Cedar Park, TX (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/31 (2020.01); G06F 30/3947 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3947 (2020.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01);
Abstract
Various embodiments provide for detecting and modeling vias of a circuit design during global routing, which may be part of electronic design automation (EDA). In particular, various embodiments described herein detect and model a big via during a global routing process, which can help mitigate or avoid minimum spacing violations by big vias.