The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Apr. 28, 2023
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Yi-Xiao Ding, Austin, TX (US);

Zhuo Li, Austin, TX (US);

Charles Jay Alpert, Cedar Park, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/396 (2020.01); G06F 30/347 (2020.01);
U.S. Cl.
CPC ...
G06F 30/396 (2020.01); G06F 30/347 (2020.01);
Abstract

Aspects of the present disclosure include system, methods, and software for creating an H-tree routing layout. In one example, a method includes an H-tree routing layout that has a plurality of vertical traces and horizontal traces connecting a clock source to a plurality of clock sinks. The method positions a plurality of candidate buffers in the H-tree routing layout. The method assigns a 4-dimensional (4D) vector to each candidate buffer of the plurality of candidate buffers, and derives one or more merge buffer combinations from the plurality of candidate buffers based on the assigned 4D vector of at least two candidate buffers of the plurality of candidate buffers. The method also applies a threshold vector to select one or more final candidate buffers from the merge buffer combinations.


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