The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12730958 B1

Date of Patent:

Sep. 08, 2026

Filed:

Sep. 06, 2023

Non-critical child node-based insertion delay optimization in circuit design

Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Necati Uysal, Austin, TX (US);

Sheiny Fabre Almeida, Sao Jose, BR;

Natarajan Viswanathan, Austin, TX (US);

Charles Jay Alpert, Cedar Park, TX (US);

Amin Farshidi, Austin, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:

Schwegman Lundberg & Woessner, P.A.

Primary Examiner:

Brian Ngo

Int. Cl.

CPC ...

G06F 30/30 (2020.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01);

U.S. Cl.

CPC ...

G06F 30/396 (2020.01); G06F 30/398 (2020.01);

Abstract

Various embodiments provide for optimizing (e.g., reducing) insertion delay in a circuit design based on one or more non-critical child nodes of a critical node of a routing tree, which can be performed by an electronic design automation (EDA) software to optimize (e.g., reduce) insertion delay in a clock tree of a circuit design.

Find Patent Forward Citations

Uysal, Necati. (2026). Non-critical child node-based insertion delay optimization in circuit design (U.S. Patent No. 12730958). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12730958

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