The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2025
Filed:
Jun. 02, 2022
Cadence Design Systems, Inc., San Jose, CA (US);
Derong Liu, Austin, TX (US);
Wing-Kai Chow, Austin, TX (US);
Mehmet Can Yildiz, Austin, TX (US);
Charles Jay Alpert, Cedar Park, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Aspects of the present disclosure address systems and methods for timing-based layer assignment. Routing is performed on a set of nets of an integrated circuit design. The routing comprises generating a route between a first pin and a second pin of a net. An initial layer assignment is performed on the set of nets based on the routing. The initial layer assignment comprises assigning the route to a first layer of the design based on first preferred routing layer designation. Timing-based layer assignment is performed based on the initial layer assignment. The timing-based layer assignment comprises reassigning the route from the first layer to a second layer based on a second preferred routing layer designation determined based on a comparison of a first delay value associated with the first layer and a second delay value associated with the second preferred routing layer designation.