The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2025
Filed:
Jun. 21, 2022
Cadence Design Systems, Inc., San Jose, CA (US);
Derong Liu, Austin, TX (US);
Mehmet Can Yildiz, Austin, TX (US);
Charles Jay Alpert, Cedar Park, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Aspects of the present disclosure address systems and methods for layer trimming based on resistance and capacitance (RC) values. Data describing an integrated circuit (IC) design is accessed. The IC design comprises a net and a set of routing layers. A first and second list are generated based on the set of layers. The first list comprises horizontal routing layers and the second list comprises vertical routing layers from the set of routing layers. A permitted range of RC values for routing layers in the IC design are determined. The first and second lists are filtered based on the permitted range of RC values. The first and second filtered lists are merged to create a third list of routing layers. The net is assigned to one or more routing layers selected from the third list for routing purposes.