The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Oct. 07, 2022
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Derong Liu, Austin, TX (US);
Wing-Kai Chow, Austin, TX (US);
Mehmet Can Yildiz, Austin, TX (US);
Charles Jay Alpert, Cedar Park, TX (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3947 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3947 (2020.01);
Abstract
Various embodiments provide for assigning portions of a net based on one or more non-default design rules, which may be part of electronic design automation (EDA). For example, a net of a circuit design can be a clock network, and the assigning can comprise a layer assignment process, a track assignment process, or both. Additionally, various embodiments described herein can permit a plurality of non-default design rules to be applied to a single net of a circuit design.