Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis

Abstract

Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, wherein the clock signal layout comprises a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, and creating a plurality of buffering solutions, wherein each buffering solution of the plurality of buffering solutions comprises a plurality of buffers inserted on one or more net segments of plurality of net segments. The method further includes assigning each buffering solution a timing delay value and an area value, and selecting a buffering solution of the plurality of buffering solutions based on the timing delay value and the area value. The method additionally includes committing the selected buffering solution into an integrated circuit design comprising the clock signal network.