Skewing level limited clock tree

Abstract

Methods and systems for performing post clock tree synthesis of a clock tree. The methods and systems access, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks, each clock sink in the plurality of clock sinks having an associated target insertion delay adjustment, the clock tree comprising a restriction on a quantity of levels of components for respectively adding delay to the clock source. The methods and systems identify an individual target insertion delay adjustment associated with an individual clock sink of the plurality of clock sinks and compare the individual target insertion delay adjustment to a threshold value. The methods and systems selectively remove the restriction on the quantity of levels of components to provide the individual target insertion delay adjustment based on comparing the individual target insertion delay adjustment to the threshold value.