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Santa Clara, CA, United States of America

Intel Ndtm US LLC

USPTO Granted Patents = 52

EPO Patents = 9

Forward Citations = 1

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138 inventors (with patents filed for the assignee):

Aliasgar S Madraswala (12 out of 64 patents)

Sagar Upadhyay (9 out of 16 patents)

Shantanu R Rajwade (8 out of 38 patents)

4. Narayanan Ramanan (7 out of 10 patents)

5. Rohit Sudhir Shenoy (6 out of 26 patents)

6. Richard M Fastow (5 out of 93 patents)

7. Tarek Ahmed Ameen Beshari (5 out of 9 patents)

8. Krishna Kumar Parat (5 out of 128 patents)

9. Ali Khakifirooz (4 out of 760 patents)

10. Deepak Thimmegowda (4 out of 31 patents)

11. Chang Wan Ha (4 out of 65 patents)

12. Xin Sun (4 out of 7 patents)

13. Naveen Prabhu Vittal Prabhu (4 out of 7 patents)

14. Liu Liu (4 out of 9 patents)

15. Guangyu Huang (3 out of 34 patents)

Core Competencies:

3D NAND

Storage Devices

Read Operations

Memory Arrays

Program Verification

Voltage Modulation

Defect Management

Sensing Circuits

Non-Volatile Memory

Data Structures

Circuit Characterization

52 patents: Sort by Forward Citations

1. 12743229 - Early read operation for storage devices with independent planes and plane groups (2026-09-22),

2. 12740064 - Low-cost mask punch flow (2026-09-15),

3. 12733169 - Barrier and thin spacer for 3D-NAND complementary metal-oxide semiconductor under array (2026-09-08),

4. 12713902 - ENGINEERED DIELECTRIC PROFILE FOR HIGH ASPECT-RATIO 3D NAND STRUCTURES (2026-08-18),

5. 12688896 - Deck reset read (2026-07-21),

6. 12642128 - Three-dimensional (3D) NAND component with control circuitry across multiple wafers (2026-05-26),

7. 12640209 - Modulation of source voltage in NAND-flash array read (2026-05-26),

8. 12633359 - Fast and efficient verify recovery and array discharge for 3D NAND memory arrays (2026-05-19),

9. 12625785 - Persistent data structure to track and manage SSD defects (2026-05-12),

10. 12625180 - Diagnostic ring oscillator circuit for DC and transient characterization (2026-05-12),

11. 12580018 - Additional silicide layer on top of staircase for 3D NAND WL contact connection (2026-03-17),

12. 12573454 - Power efficient array discharge for program boosting (2026-03-10),

13. 12568618 - Selective etch stop for wordline contacts in vertical 3D NAND staircase regions (2026-03-03),

14. 12564010 - Chuck with non-flat shaped surface (2026-02-24),

15. 12563725 - Parallel staircase 3D NAND (2026-02-24),

Intel Ndtm US LLC is a leading provider of non-destructive testing solutions for a wide range of industries such as aerospace, automotive, and manufacturing. With a focus on innovation and quality, Intel Ndtm US LLC offers a comprehensive suite of services including ultrasonic testing, visual inspection, and radiography. Their team of experts is dedicated to providing accurate and reliable testing to ensure the safety and integrity of critical assets.

Profile summary based on public USPTO records.

Company Badge

USPTO Data Jan 1 1976 - Sep 29 2026

52 Patents

#71 in Santa Clara, CA

#1,588 in California

#6,757 in US

#13,537 in the World

Santa Clara, CA, United States of America

Intel Ndtm US LLC

Forward Citations = 1

138 inventors:

Aliasgar S Madraswala (12 out of 64 patents)

Sagar Upadhyay (9 out of 16 patents)

Shantanu R Rajwade (8 out of 38 patents)

4. Narayanan Ramanan (7 out of 10 patents)

5. Rohit Sudhir Shenoy (6 out of 26 patents)

Please report any incorrect information to [email protected]

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