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Santa Clara, CA, United States of America

Intel Ndtm US LLC

USPTO Granted Patents = 33

EPO Patents = 5

Forward Citations = 1

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88 inventors (with patents filed for the assignee):

Aliasgar S Madraswala (8 out of 59 patents)

Sagar Upadhyay (7 out of 14 patents)

Narayanan Ramanan (6 out of 9 patents)

4. Shantanu R Rajwade (5 out of 34 patents)

5. Guangyu Huang (3 out of 34 patents)

6. Richard M Fastow (3 out of 91 patents)

7. Tarek Ahmed Ameen Beshari (3 out of 7 patents)

8. Matin Amani (3 out of 4 patents)

9. Naveen Prabhu Vittal Prabhu (3 out of 6 patents)

10. Krishna Kumar Parat (3 out of 126 patents)

11. Bhaskar Venkataramaiah (3 out of 3 patents)

12. Ahsanur Rahman (3 out of 3 patents)

13. Ali Khakifirooz (2 out of 757 patents)

14. Deepak Thimmegowda (2 out of 29 patents)

15. Chang Wan Ha (2 out of 62 patents)

33 patents: Sort by Forward Citations

1. 12512407 - Stitching to enable dense interconnect arrangements (2025-12-30),

2. 12500122 - Interdeck layers and pillar alignment (2025-12-16),

3. 12488819 - Dummy wordline contacts to improve etch margin of semi-isolated wordlines in staircase structures (2025-12-02),

4. 12488817 - Enhanced IO interface for plc program and program-suspend-resume operations (2025-12-02),

5. 12484225 - Metal hybrid charge storage structure for memory (2025-11-25),

6. 12468484 - Express status operation for storage devices with independent planes and plane groups (2025-11-11),

7. 12467974 - Diagnostic ring oscillator circuit for DC and transient characterization (2025-11-11),

8. 12461654 - Method of detecting read hotness and degree of randomness in solid-state drives (SSDS) (2025-11-04),

9. 12432922 - Method and apparatus to mitigate word line staircase etch stop layer thickness variations in 3D NAND devices (2025-09-30),

10. 12424483 - 3D NAND with inter-wordline airgap (2025-09-23),

11. 12394497 - Efficient bitline stabilization for program inhibit in NAND arrays (2025-08-19),

12. 12394492 - Memory cell sensing circuit with adjusted bias from pre-boost operation (2025-08-19),

13. 12393367 - Lean command sequence for multi-plane read operations (2025-08-19),

14. 12379989 - Zero voltage program state detection (2025-08-05),

15. 12362016 - Read latency reduction for partially-programmed block of non-volatile memory (2025-07-15),

Intel Ndtm US LLC is a leading provider of non-destructive testing solutions for a wide range of industries such as aerospace, automotive, and manufacturing. With a focus on innovation and quality, Intel Ndtm US LLC offers a comprehensive suite of services including ultrasonic testing, visual inspection, and radiography. Their team of experts is dedicated to providing accurate and reliable testing to ensure the safety and integrity of critical assets.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 30 2025

33 Patents

#138 in Santa Clara, CA

#2,382 in California

#9,948 in US

#19,556 in the World

Santa Clara, CA, United States of America

Intel Ndtm US LLC

Forward Citations = 1

88 inventors:

Aliasgar S Madraswala (8 out of 59 patents)

Sagar Upadhyay (7 out of 14 patents)

Narayanan Ramanan (6 out of 9 patents)

4. Shantanu R Rajwade (5 out of 34 patents)

5. Guangyu Huang (3 out of 34 patents)

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