The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Mar. 29, 2024
Applicant:

Intel Ndtm Us Llc, Santa Clara, CA (US);

Inventors:

Andreas Kerber, Pleasanton, CA (US);

Phillip Kliza, Folsom, CA (US);

Assignee:

INTEL NDTM US LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/319 (2006.01); G01R 31/26 (2020.01); H03K 3/03 (2006.01); H03K 3/354 (2006.01); H03K 17/687 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31915 (2013.01); G01R 31/2626 (2013.01); G01R 31/31905 (2013.01); H03K 3/0315 (2013.01); H03K 3/354 (2013.01); H03K 17/6872 (2013.01); H03K 19/018521 (2013.01); H03K 2217/0054 (2013.01);
Abstract

A ring oscillator (RO) circuit for capturing one or more characteristics relating to aging of CMOS circuitry in a CMOS device has been described. The RO circuit includes a plurality of stages coupled via an RO feedback signal line and forming an inverter chain. The plurality of stages include, for each stage, a respective CMOS inverter comprising a pair of pMOS and nMOS transistors followed by a pass gate, wherein an output of a pass gate for a stage is coupled to an input for the respective CMOS inverter of a next stage. The plurality of stages include an enable stage to enable the inverter chain to be put into a free oscillating mode or another mode in which the RO circuit does not freely oscillate. The plurality of stages include a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and pre-stage are isolated from one another.


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