The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2026
Filed:
Dec. 23, 2023
Intel Ndtm Us Llc, Santa Clara, CA (US);
Chao Zhang, Milpitas, CA (US);
Xin Sun, Fremont, CA (US);
Richard Fastow, Cupertino, CA (US);
Giuseppina Puzzilli, Boise, ID (US);
Krishna K. Parat, Palo Alto, CA (US);
INTEL NDTM US LLC, Santa Clara, CA (US);
Abstract
A storage device includes a storage array having multiple decks of NAND cells in a three dimensional (3D) stack. There can be any number of decks that have multiple wordlines in vertical stacks. The decks include a first deck and a second deck. Bias circuitry can apply different voltages to different decks of the storage array. The bias circuitry can apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.