The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2026
Filed:
Dec. 19, 2022
Applicant:
Intel Ndtm Us Llc, Santa Clara, CA (US);
Inventors:
Sriram Balasubrahmanyam, Folsom, CA (US);
Tri Tran, Elk Grove, CA (US);
Jong Tai Park, Pleasanton, CA (US);
Priyanka Ravindran, San Jose, CA (US);
Chuc Thanh, Davis, CA (US);
Assignee:
Intel NDTM US LLC, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/32 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H03K 3/017 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 16/32 (2013.01); G06F 3/061 (2013.01); G06F 3/0629 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H03K 3/017 (2013.01); G11C 29/023 (2013.01);
Abstract
An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to provide duty cycle correction (DCC) for one or more write paths of the NAND memory. Other examples are disclosed and claimed.
Quick Actions:
Balasubrahmanyam, Sriram. (2026). Nand duty cycle correction for data input write path (U.S. Patent No. 12784842). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12784842
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile