Word line voltage detection circuit for enhanced read operation

Abstract

Technology herein provides a performance-enhanced memory device including a memory array including a local word line circuit and a plurality of local word lines coupled to the local word line circuit, a word line (WL) sense circuit coupled to an access node in the local word line circuit, the WL sense circuit to sense a voltage level in the local word line circuit while bypassing a disturbance to operation of the local word lines and to provide an output signal that indicates when the voltage level has reached a high voltage threshold value to enable a read operation. The technology also provides read logic coupled to the WL sense circuit, the read logic to receive the output signal from the WL sense circuit, and trigger a read operation for one or more cells in the memory array when the output signal indicates that the voltage level has reached the high voltage threshold value.