The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
May. 12, 2023
Intel Ndtm Us Llc, Santa Clara, CA (US);
INTEL NDTM US LLC, Santa Clara, CA (US);
Abstract
Methods and apparatus for low-cost punch through flows. Pillar recesses are formed in a semiconductor structure comprising a stack of layers. A negative photoresist coating is applied over regions containing the plurality of pillar recesses. Using a mask, the negative photoresist is in regions in which dummy pillars are to be formed to causing the negative photoresist to polymerize and become insoluble to a developer. A developer is then applied to the semiconductor structure to dissolve the negative photoresist in the pillar recesses that are not exposed. A punch through operation is then performed using an etchant to punch through the bottoms of the pillar recesses that are not covered by the polymerized photoresist, while the bottoms of the pillar recesses that are covered are not punched through. The semiconductor process flow may be used in memory device, such as but not limited to 3D NAND devices.