Dalian, China

Xin Fu

This inventor holds 1 USPTO granted patent. Top assignee: Intel Ndtm US LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Xin Fu. Retrieved from https://idiyas.com/inventor/xin-fu-q2u6eyj0

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Xin Fu and Semiconductor Process Innovation.

Introduction

Xin Fu is an inventor associated with Dalian, China, and Intel NDTM US LLC. His patent work describes a semiconductor fabrication method intended to support low-cost punch-through processing.

Latest Patents

The provided information lists one patent for Xin Fu: “Methods and Apparatus for Low-Cost Punch Through Flows.” The method forms pillar recesses in a semiconductor structure made from a stack of layers, then applies negative photoresist. A mask exposes selected regions where dummy pillars are intended, polymerizing the resist in those areas. After development removes unexposed resist from other recesses, an etchant punches through the uncovered recess bottoms while leaving the protected bottoms intact. The process may be used in memory devices, including 3D NAND devices. The listed patent count is 1 patent.

Career Highlights

The described invention focuses on selectively controlling punch-through etching through patterned photoresist. This approach is presented as a way to simplify semiconductor processing and reduce costs. The supplied information identifies Intel NDTM US LLC as Fu’s company affiliation.

Collaborations

Peng Li and Prasanna Srinivasan are identified as Fu’s coworkers. The available details do not specify their roles in the patent or the development of the process.

Conclusion

Xin Fu’s listed patent addresses selective punch-through processing for semiconductor structures, with potential application in memory technologies such as 3D NAND.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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