For the Inventor, By the Inventor

Enter assignee name

Singapore, Singapore

Chartered Semiconductor Manufacturing Ltd (corporation)

USPTO Granted Patents = 962

EPO Patents = 2

Forward Citations = 15,758

Loading Chart...

Loading Chart...

921 inventors (with patents filed for the assignee):

Lap Chan (127 out of 149 patents)

Mei Sheng Zhou (90 out of 108 patents)

Simon Yew-Meng Chooi (88 out of 94 patents)

4. Jia Zhen Zheng (79 out of 81 patents)

5. Yelehanka Ramachandramurthy Pradeep (57 out of 59 patents)

6. Yang Pan (57 out of 73 patents)

7. Subhash Gupta (50 out of 86 patents)

8. Elgin Kiok Quek (49 out of 107 patents)

9. Alex See (47 out of 84 patents)

10. John Leonard Sudijono (42 out of 68 patents)

11. Liang Choo Hsia (40 out of 66 patents)

12. Ting Cheong Ang (37 out of 38 patents)

13. Mei-Sheng Zhou (34 out of 37 patents)

14. Yi Liang Xu (33 out of 36 patents)

15. Purakh Raj Verma (32 out of 144 patents)

Core Competencies:

Silicide Technology

Field Effect Transistors

Strain Engineering

Epitaxial Growth

CMOS Devices

Interconnect Structures

Stress Optimization

Integrated Circuits

Dielectric Materials

Device Fabrication

Electrical Overstress Protection

Thin Film Etching

962 patents: Sort by Forward Citations

1. 8643119 - Substantially L-shaped silicide for contact (2014-02-04),

2. 8623714 - Spacer protection and electrical connection for array device (2014-01-07),

3. 8461009 - Spacer and process to enhance the strain in the channel with stress liner (2013-06-11),

4. 8236699 - Contact patterning method with transition etch feedback (2012-08-07),

5. 8198194 - Methods of forming p-channel field effect transistors having SiGe source/drain regions (2012-06-12),

6. 8138055 - Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same (2012-03-20),

7. 8106462 - Balancing NFET and PFET performance using straining layers (2012-01-31),

8. 8058176 - Methods of patterning insulating layers using etching techniques that compensate for etch rate variations (2011-11-15),

9. 8026166 - Interconnect structures comprising capping layers with low dielectric constants and methods of making the same (2011-09-27),

10. 8017472 - CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof (2011-09-13),

11. 8012839 - Method for fabricating a semiconductor device having an epitaxial channel and transistor having same (2011-09-06),

12. 7994010 - Process for fabricating a semiconductor device having embedded epitaxial regions (2011-08-09),

13. 7977185 - Method and apparatus for post silicide spacer removal (2011-07-12),

14. 7960283 - Method for reducing silicide defects in integrated circuits (2011-06-14),

15. 7955936 - Semiconductor fabrication process including an SiGe rework method (2011-06-07),

Chartered Semiconductor Manufacturing Ltd is a leading global semiconductor foundry company based in Singapore. They offer advanced wafer fabrication solutions and manufacturing services to various industries, including consumer electronics, automotive, telecommunications, and more. With a strong commitment to technology innovation and quality, Chartered Semiconductor Manufacturing Ltd provides customers with reliable and cost-effective solutions to meet their semiconductor needs.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 9 2025

962 Patents

#7 in Singapore

#7 in Singapore

#1,032 in the World

Singapore, Singapore

Chartered Semiconductor Manufacturing Ltd (corporation)

Forward Citations = 15,758

921 inventors:

Lap Chan (127 out of 149 patents)

Mei Sheng Zhou (90 out of 108 patents)

Simon Yew-Meng Chooi (88 out of 94 patents)

4. Jia Zhen Zheng (79 out of 81 patents)

5. Yelehanka Ramachandramurthy Pradeep (57 out of 59 patents)

Please report any incorrect information to support@idiyas.com

Loading…