The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2014
Filed:
Mar. 22, 2010
Jae-eun Park, Hopewell Junction, NY (US);
Weipeng LI, Hopewell Junction, NY (US);
Deleep R. Nair, Hopewell Junction, NY (US);
M. Dean Sciacca, Hopewell Junction, NY (US);
Voon-yew Thean, Hopewell Junction, NY (US);
Ava Wan, Hopewell Junction, NY (US);
Dong-hun Lee, Hopewell Junction, NY (US);
Yong-meng Lee, Hopewell Junction, NY (US);
Jae-Eun Park, Hopewell Junction, NY (US);
Weipeng Li, Hopewell Junction, NY (US);
Deleep R. Nair, Hopewell Junction, NY (US);
M. Dean Sciacca, Hopewell Junction, NY (US);
Voon-Yew Thean, Hopewell Junction, NY (US);
Ava Wan, Hopewell Junction, NY (US);
Dong-Hun Lee, Hopewell Junction, NY (US);
Yong-Meng Lee, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Chartered Semiconductor Manufacturing, Ltd., Singapore, SG;
Abstract
The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.