Fishkill, NY, United States of America

Deleep R Nair

This inventor holds 12 USPTO granted patents. Top assignees: International Business Machines Corporation, Globalfoundries Inc., Chartered Semiconductor Manufacturing Ltd (Corporation). Active years: 2009-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Deleep R Nair. Retrieved from https://idiyas.com/inventor/deleep-r-nair

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.3

ph-index = 4

Forward Citations = 40(Granted Patents)


Location History:

  • Wappingers Falls, NY (US) (2009 - 2011)
  • Hopewell Junction, NY (US) (2014)
  • Fishkill, NY (US) (2012 - 2016)

Company Filing History:


Years Active: 2009-2016

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12 patents (USPTO):Explore Patents

Title: Innovator Spotlight: Deleep R. Nair

Introduction

Deleep R. Nair, based in Fishkill, NY, is a prolific inventor with an impressive portfolio of 12 patents. His work primarily revolves around advancements in semiconductor technologies, focusing on the interaction between materials and their electrical properties.

Latest Patents

Among his latest innovations are the following patents:

1. **Method and Structure to Reduce FET Threshold Voltage Shift Due to Oxygen Diffusion**: This patent describes an oxygen scavenging material embedded in an isolation structure that enhances the protection of high dielectric constant (Hi-K) materials from oxygen contamination. This invention is pivotal in maintaining the integrity of transistors utilizing such materials by preventing alteration of the work function and shifting the switching threshold.

2. **Oxygen Scavenging Spacer for a Gate Electrode**: This patent presents a design where at least one layer consisting of scavenging and dielectric materials is deposited over a gate stack. The anisotropic etching of this layer forms a gate spacer that incorporates oxygen scavenging materials. The invention features techniques to distribute the scavenging material within the gate spacer to prevent electrical shorts between the gate electrode and the underlying semiconductor material, while actively scavenging oxygen diffusing toward the gate dielectric.

Career Highlights

Deleep has had a distinguished career working for leading companies in semiconductor technology, including International Business Machines Corporation (IBM) and Globalfoundries Inc. His contributions significantly advance the capabilities of transistor technology, particularly in environments sensitive to oxygen contamination.

Collaborations

Throughout his career, Deleep R. Nair has collaborated with prominent researchers such as Jae-Eun Park and Weipeng Li, furthering innovations in the field of semiconductor materials and devices.

Conclusion

With a strong focus on overcoming challenges related to oxygen contamination in semiconductor materials, Deleep R. Nair continues to be at the forefront of innovation. His pioneering patents reflect a dedication to enhancing the performance and reliability of advanced electronic devices, marking him as a significant contributor to the field of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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