The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7863112 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 04, 2011

Filed:

Jan. 08, 2008
Applicants:

Deleep R. Nair, Wappingers Falls, NY (US);

Terence B. Hook, Jericho, VT (US);

Inventors:

Deleep R. Nair, Wappingers Falls, NY (US);

Terence B. Hook, Jericho, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8283 (2006.01);
U.S. Cl.
CPC ...
Abstract

Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate oxide of the FET, has a gate structure (poly) connected with the gate of the FET, and may be shorted out by the first metal layer (M).


Find Patent Forward Citations

Nair, Deleep. (2011). Method and structure to protect fets from plasma damage during feol processing (U.S. Patent No. 7863112). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7863112

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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