The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Mar. 23, 2012
Xiangdong Chen, Poughquag, NY (US);
Jie Deng, Wappingers Falls, NY (US);
Weipeng LI, Beacon, NY (US);
Deleep R. Nair, Fishkill, NY (US);
Jae-eun Park, Wappingers Falls, NY (US);
Daniel Tekleab, Wappingers Falls, NY (US);
Xiaobin Yuan, Carmel, NY (US);
Nam Sung Kim, Hopewell Junction, NY (US);
Xiangdong Chen, Poughquag, NY (US);
Jie Deng, Wappingers Falls, NY (US);
Weipeng Li, Beacon, NY (US);
Deleep R. Nair, Fishkill, NY (US);
Jae-Eun Park, Wappingers Falls, NY (US);
Daniel Tekleab, Wappingers Falls, NY (US);
Xiaobin Yuan, Carmel, NY (US);
Nam Sung Kim, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Globalfoundries Inc., Grand Cayman, KY;
Abstract
A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.