Sanjay C Mehta

USPTO Granted Patents = 122 (Patent Applications = 17)

Average Co-Inventor Count = 4.2

ph-index = 11

Forward Citations = 620(Granted Patents)

Forward Citations (Not Self Cited) = 585(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Slingerlands, NY (US) (2010)
Poughkeepsie, NY (US) (2007 - 2011)
Albany, NY (US) (2012 - 2014)
Niskayuna, NY (US) (2010 - 2023)

Company Filing History:

114 out of 164,135

International Business Machines Corporation

Stmicroelectronics Gmbh

patents

4. 1 out of 238

Renesas Electronics America Inc.

patents

5. 1 out of 1,853

Adeia Semiconductor Bonding Technologies Inc.

patents

6. 1 out of 20

Adeia Semiconductor Solutions LLC

patents

where one patent can have more than one assignee

Years Active: 2007-2025

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Areas of Expertise:

Nanosheet Devices

Phase Change Memory

Vertical Transistors

Field Effect Transistors

High-K Dielectric

Doped Silicon Gates

Epitaxial Source/Drain

Semiconductor Fabrication

Thermal Budget Integration

Device Spacers

Fin Field Effect Transistors

Aggressive Fin-Pitch Scaling

122 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12250835 - Isolation between vertically stacked nanosheet devices (2025-03-11),

2. 12224203 - Air gap spacer formation for nano-scale semiconductor devices (2025-02-11),

3. 11658062 - Air gap spacer formation for nano-scale semiconductor devices (2023-05-23),

4. 11456415 - Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner (2022-09-27),

5. 11302797 - Approach to bottom dielectric isolation for vertical transport fin field effect transistors (2022-04-12),

6. 11264569 - Phase change memory device (2022-03-01),

7. 11171204 - High thermal budget compatible punch through stop integration using doped glass (2021-11-09),

8. 11152460 - High thermal budget compatible punch through stop integration using doped glass (2021-10-19),

9. 10892339 - Gate first technique in vertical transport FET using doped silicon gates with silicide (2021-01-12),

10. 10879375 - Gate tie-down enablement with inner spacer (2020-12-29),

11. 10840354 - Approach to bottom dielectric isolation for vertical transport fin field effect transistors (2020-11-17),

12. 10784371 - Self aligned top extension formation for vertical transistors (2020-09-22),

13. 10784258 - Selective contact etch for unmerged epitaxial source/drain regions (2020-09-22),

14. 10707326 - Vertical field-effect-transistors having a silicon oxide layer with controlled thickness (2020-07-07),

15. 10692985 - Protection of high-K dielectric during reliability anneal on nanosheet structures (2020-06-23),

Title: Sanjay C Mehta - Pioneering Inventor from Niskayuna, NY

Introduction: Sanjay C Mehta is a distinguished inventor based in Niskayuna, NY, known for his groundbreaking contributions to the field of innovations and patents.

Latest Patents: Sanjay C Mehta holds several patents in various technological domains, showcasing his versatility and ingenuity in inventing novel solutions to complex problems.

Career Highlights: With a career spanning over two decades, Sanjay C Mehta has worked tirelessly to push the boundaries of technological advancements. His innovative spirit and dedication have led to the development of cutting-edge solutions that have made a significant impact in the industry.

Collaborations: Throughout his career, Sanjay C Mehta has collaborated with leading research institutions, universities, and companies to bring his inventions to life. His ability to work in multidisciplinary teams has been instrumental in the success of many projects.

Conclusion: Sanjay C Mehta's passion for innovation, coupled with his technical expertise, has established him as a prominent figure in the world of inventions and patents. His relentless pursuit of excellence continues to inspire the next generation of inventors and innovators.

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17 patents pending:

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