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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10784371 B1

PDFFull Text
Date of Patent:
Sep. 22, 2020

Filed:

Aug. 29, 2019

Self aligned top extension formation for vertical transistors

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Oleg Gluschenkov, Tannersville, NY (US);

Sanjay C. Mehta, Niskayuna, NY (US);

Shogo Mochizuki, Clifton Park, NY (US);

Alexander Reznicek, Troy, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C.

Daniel Morris

Primary Examiner:

Samuel A Gebremariam

Int. Cl.
CPC ...
H01L 31/072 (2012.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/0257 (2013.01); H01L 21/26506 (2013.01); H01L 21/30604 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/66666 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 29/165 (2013.01);
Abstract

A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

Find Patent Forward Citations

Gluschenkov, Oleg. (2020). Self aligned top extension formation for vertical transistors (U.S. Patent No. 10784371). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10784371

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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