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San Jose, CA, United States of America

Adeia Semiconductor Solutions LLC

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USPTO Granted Patents = 30

EPO Patents = 1

Forward Citations = 3

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87 inventors (with patents filed for the assignee):

Kangguo Cheng (13 out of 2,871 patents)

Benjamin David Briggs (5 out of 198 patents)

Lawrence Alfred Clevenger (4 out of 710 patents)

4. Fee Li Lie (3 out of 178 patents)

5. Christopher J Penny (3 out of 172 patents)

6. Peng Xu (3 out of 356 patents)

7. Balasubramanian Pranatharthiharan (3 out of 217 patents)

8. John R Sporre (3 out of 3 patents)

9. Junli Wang (2 out of 483 patents)

10. Huai Huang (2 out of 62 patents)

11. Ilyas Mohammed (2 out of 285 patents)

12. Belgacem Haba (2 out of 674 patents)

13. Juntao Li (2 out of 579 patents)

14. Michael Rizzolo (2 out of 211 patents)

15. Takeshi Nogami (2 out of 196 patents)

Core Competencies:

Nanosheet Transistor

FinFET

3D Capacitors

Electromigration

Self-Aligned Vias

Air Gap Formation

Copper Interconnects

Manganese Barrier Layer

Selective Gas Etching

Dual Channel Devices

Porous Dielectric Layer

Asymmetrical Ion Bombardment

30 patents: Sort by Forward Citations

1. 12690251 - Method of forming nanosheet field effect transistors with partial inside spacers (2026-07-21),

2. 12685112 - Method of forming copper interconnect structure with manganese barrier layer (2026-07-14),

3. 12628628 - Structure and method to improve FAV RIE process margin and electromigration (2026-05-12),

4. 12622003 - High density three-dimensional integrated capacitors (2026-05-05),

5. 12598786 - Field effect transistor structures (2026-04-07),

6. 12550709 - Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device (2026-02-10),

7. 12550359 - Forming a sacrificial liner for dual channel devices (2026-02-10),

8. 12532682 - Method of manufacturing a structure by asymmetrical ion bombardment of a capped underlying layer (2026-01-20),

9. 12520567 - Hybrid-channel nano-sheet FETs (2026-01-06),

10. 12494453 - Package-on-package assembly with wire bonds to encapsulation surface (2025-12-09),

11. 12488986 - Selective gas etching for self-aligned pattern transfer (2025-12-02),

12. 12482704 - Self-forming barrier for use in air gap formation (2025-11-25),

13. RE50613 - FinFET gate cut after dummy gate removal (2025-09-30),

14. 12402403 - Air gap spacer for metal gates (2025-08-26),

15. 12387983 - Forming self-aligned vias and air-gaps in semiconductor fabrication (2025-08-12),

Company Overview

Adeia Semiconductor Solutions LLC, based in San Jose, California, specializes in advanced semiconductor technologies that drive innovation across various industries. The company focuses on developing cutting-edge solutions that enhance performance and efficiency in electronic devices. With a strong emphasis on research and development, Adeia is dedicated to pushing the boundaries of semiconductor applications, contributing to advancements in areas such as telecommunications, consumer electronics, and automotive systems.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Nov 3 2026

30 Patents

#264 in San Jose, CA

#2,688 in California

#11,291 in US

#21,929 in the World

San Jose, CA, United States of America

Adeia Semiconductor Solutions LLC

Forward Citations = 3

87 inventors:

Kangguo Cheng (13 out of 2,871 patents)

Benjamin David Briggs (5 out of 198 patents)

Lawrence Alfred Clevenger (4 out of 710 patents)

4. Fee Li Lie (3 out of 178 patents)

5. Christopher J Penny (3 out of 172 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Adeia Semiconductor Solutions LLC. Retrieved from https://idiyas.com/company/adeia-semiconductor-solutions

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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