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San Jose, CA, United States of America

Adeia Semiconductor Solutions LLC

USPTO Granted Patents = 20

EPO Patents = 1

Forward Citations = 0

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70 inventors (with patents filed for the assignee):

Kangguo Cheng (10 out of 2,833 patents)

Fee Li Lie (3 out of 175 patents)

Balasubramanian Pranatharthiharan (3 out of 214 patents)

4. Lawrence Alfred Clevenger (3 out of 645 patents)

5. Benjamin D Briggs (3 out of 4 patents)

6. John R Sporre (3 out of 3 patents)

7. Junli Wang (2 out of 438 patents)

8. Christopher J Penny (2 out of 167 patents)

9. Juntao Li (2 out of 551 patents)

10. Sean Teehan (2 out of 70 patents)

11. Charan V Surisetty (2 out of 38 patents)

12. Eric R Miller (2 out of 84 patents)

13. John H Zhang (2 out of 218 patents)

14. Sean D Burns (2 out of 3 patents)

15. Marc A Bergendahl (2 out of 3 patents)

20 patents: Sort by Forward Citations

1. 12494453 - Package-on-package assembly with wire bonds to encapsulation surface (2025-12-09),

2. 12488986 - Selective gas etching for self-aligned pattern transfer (2025-12-02),

3. 12482704 - Self-forming barrier for use in air gap formation (2025-11-25),

4. RE50613 - FinFET gate cut after dummy gate removal (2025-09-30),

5. 12402403 - Air gap spacer for metal gates (2025-08-26),

6. 12387983 - Forming self-aligned vias and air-gaps in semiconductor fabrication (2025-08-12),

7. 12376369 - FinFET devices (2025-07-29),

8. 12369379 - Nanosheet transistor (2025-07-22),

9. 12369367 - Bulk nanosheet with dielectric isolation (2025-07-22),

10. 12327730 - Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic (2025-06-10),

11. 12322601 - Alternating hardmasks for tight-pitch line formation (2025-06-03),

12. 12237368 - Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack (2025-02-25),

13. 12237328 - Minimizing shorting between FinFET epitaxial regions (2025-02-25),

14. 12230544 - Stacked transistors with different channel widths (2025-02-18),

15. 12224203 - Air gap spacer formation for nano-scale semiconductor devices (2025-02-11),

Adeia Semiconductor Solutions LLC specializes in advanced semiconductor technologies, focusing on innovative solutions for a wide range of electronic applications. By leveraging cutting-edge design methodologies and manufacturing processes, the company aims to enhance performance and efficiency in semiconductor devices. Adeia's expertise spans various sectors including telecommunications, computing, and consumer electronics. The firm is dedicated to driving advancements in silicon technology and improving the overall functionality of integrated circuits. Adeia Semiconductor Solutions LLC is committed to providing high-quality, reliable semiconductor products tailored to meet the evolving needs of modern technology.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 9 2025

20 Patents

#321 in San Jose, CA

#3,801 in California

#15,856 in US

#30,316 in the World

San Jose, CA, United States of America

Adeia Semiconductor Solutions LLC

Forward Citations = 0

70 inventors:

Kangguo Cheng (10 out of 2,833 patents)

Fee Li Lie (3 out of 175 patents)

Balasubramanian Pranatharthiharan (3 out of 214 patents)

4. Lawrence Alfred Clevenger (3 out of 645 patents)

5. Benjamin D Briggs (3 out of 4 patents)

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